(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for semiconductor devices.
(2) Description of the Prior Art
The creation of semiconductor devices, also referred to as Integrated Circuits (IC), has been made possible by the rapid development of supporting technologies such as photolithography and methods of etching. Most of these technologies have over the years addressed concerns created by a continued decrease in device dimensions and increase in device densities. This effort of creating improved performance devices is not limited to the impact on the semiconductor device but extends into the methods and packages that are used to further interconnect semiconductor devices and to protect these devices from environmental damage. This latter issue has created a packaging technology that is also driven by demands of device miniaturization and the denser packaging of devices, demands that must be met at no penalty to device performance and in a cost-effective manner.
Semiconductor device packaging typically mounts a device on a substrate, such as semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support. Such a substrate can be a relative complex structure, having multiple layers of interconnect metal distributed throughout the height of the substrate in addition to having interconnect traces created on one or both surfaces of the substrate. In addition, in order to enable the mounting of semiconductor over the surface of the substrate, contact pads such as bond pads are typically provided over at least one of the surfaces of a substrate. For more complex packages, several levels of packaging may be applied whereby a semiconductor device is mounted on a substrate and connected to interconnect metal that is part of the substrate. The first level substrate may be further mounted over the surface of a larger substrate from which the device is interconnected to surrounding circuitry or electrical components. Limitations that are imposed on this method of packaging are typically limitations of electrical performance imposed on the device by the packaging interface. For instance, of key concern is RC delay incurred in the transmission of signals over the various interconnect traces. This places a restraint on the size and therefore on the packaging density on the package. Also of concern are considerations of parasitic capacitance and inductance that are introduced by the package since these parameters have a negative impact on device performance, a more serious impact on high frequency device performance. These parasitic components must therefore be minimized or suppressed to the maximum extent possible.
One or the more conventional methods of connecting a semiconductor device to surrounding points of interconnect is the use of a solder bump. Typically a semiconductor device will be provided on the active surface of the device with points of electrical interconnect, which electrically access the device. To connect these points of interconnect to for instance a printed circuit board, solder bumps are provided on the surface of the circuit board that align with the points of electrical contact of the device. The creation of this interface is also subject to requirements that are imposed by electrical performance of the completed package, by requirements of package miniaturization, reliability, cost performance and the like. The invention provides a package that addresses these packaging concerns in addition to others.
U.S. Pat. No. 6,181,56.9 (Charkravorty) shows a solder bump process and structure that includes trace formation and bump plating.
U.S. Pat. No. 6,107,180 (Munroe et al.) shows a bump process using UBM and solder bumps.
U.S. Pat. No. 5,879,964 (Paik et al.) shows a related bump and interconnect process.
A principle objective of the invention is to provide a high-pillar solder bump that sustains a high stand-off of the complete solder bump while maintaining high bump reliability and minimizing damage caused by mismatching of thermal stress factors between the interfacing surfaces.
Another objective of the invention is to provide a method that further improves bump reliability by reducing mechanical and thermal stress.
Yet another objective of the invention is to provide re-distribution bumps which enable the creation of a flip-chip package without requiring a change in the design of the Integrated Circuit and without modifying the pad pitch, the performance of the package is improved and the package size does not need to be modified.
A still further objective of the invention is to provide a chip scale package using one UBM layer of metal, significantly reducing costs of fabrication and materials.
A still further objective of the invention is to provide a chip scale package whereby the solder ball is removed from the semiconductor device, eliminating the need for low-alpha solder, thus reducing fabrication cost and concerns of soft-error occurrence.
A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.